118 search results - page 13 / 24 » A technique for minimizing power during FPGA placement |
DSN
2008
IEEE
14 years 2 months ago
2008
IEEE
: The consolidation of multiple servers and their workloads aims to minimize the number of servers needed thereby enabling the efficient use of server and power resources. At the s...
DATE
1998
IEEE
14 years 21 days ago
1998
IEEE
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
ASPDAC
2010
ACM
13 years 6 months ago
2010
ACM
Modern digital IC designs have a critical operating point, or "wall of slack", that limits voltage scaling. Even with an errortolerance mechanism, scaling voltage below a...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
Modern applications for mobile devices, such as multimedia video/audio, often exhibit a common behavior: they process streams of incoming data in a regular, predictable way. The r...
ISSS
1999
IEEE
14 years 22 days ago
1999
IEEE
Synchronous Dataflow, a subset of dataflow, has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem duri...