77 search results - page 4 / 16 » Accurate models for estimating area and power of FPGA implem... |
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence o...
ISSS
2002
IEEE
14 years 11 days ago
2002
IEEE
We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for i...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
FPL
2008
Springer
13 years 9 months ago
2008
Springer
This paper describes an analytical model, based principally on Rent's Rule, that relates logic architectural parameters to the area efficiency of an FPGA. In particular, the ...