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ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
14 years 7 months ago
FBT: filled buffer technique to reduce code size for VLIW processors
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
Talal Bonny, Jörg Henkel
ICCAD
2007
IEEE
144views Hardware» more  ICCAD 2007»
14 years 7 months ago
Voltage island-driven floorplanning
— Energy efficiency has become one of the most important issues to be addressed in today’s System-on-a-Chip (SoC) designs. One way to lower the power consumption is to reduce ...
Qiang Ma, Evangeline F. Y. Young
ICCAD
2005
IEEE
87views Hardware» more  ICCAD 2005»
14 years 7 months ago
Statistical technology mapping for parametric yield
The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by ...
Ashish Kumar Singh, Murari Mani, Michael Orshansky
ICCAD
2003
IEEE
148views Hardware» more  ICCAD 2003»
14 years 7 months ago
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
In this paper we present a family of multi-objective hypergraph partitioning algorithms based on the multilevel paradigm, which are capable of producing solutions in which both th...
Navaratnasothie Selvakkumaran, George Karypis
ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
14 years 7 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
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