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DAC
2010
ACM
13 years 6 months ago
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation
Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates systemlev...
Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li
DAC
2008
ACM
14 years 9 months ago
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
S. Raja, F. Varadi, Murat R. Becer, Joao Geada
DAC
2003
ACM
14 years 9 months ago
Efficient model order reduction including skin effect
Skin effect makes interconnect resistance and inductance frequency dependent. This paper addresses the problem of efficiently estimating the signal characteristics of any RLC netw...
Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail
DAC
2004
ACM
14 years 9 months ago
Toward a methodology for manufacturability-driven design rule exploration
Resolution enhancement techniques (RET) such as optical proximity correction (OPC) and phase-shift mask (PSM) technology are deployed in modern processes to increase the fidelity ...
Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, De...
DAC
2006
ACM
14 years 9 months ago
Timing-driven Steiner trees are (practically) free
Traditionally, rectilinear Steiner minimum trees (RSMT) are widely used for routing estimation in design optimizations like floorplanning and physical synthesis. Since it optimize...
Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sz...
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