95 search results - page 4 / 19 » An Analog Integrated Circuit Design Laboratory |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper demonstrates a system that performs multiobjective sizing across 100,000 analog circuit topologies simultaneously, with SPICE accuracy. It builds on a previous system, ...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. However, scaling into...
DAC
2004
ACM
14 years 1 months ago
2004
ACM
Aggressive design cycles in the semiconductor industry demand a design-reuse principle for analog circuits. The strong impact of layout intricacies on analog circuit performance n...
ICCAD
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper presents ISCLEs, a novel and robust analog design method that promises to scale with Moore’s Law, by doing boosting-style importance sampling on digital-sized circuit...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...