286 search results - page 28 / 58 » An Evolutionary Approach to Area-Time Optimization of FPGA d... |
GECCO
2005
Springer
14 years 4 months ago
2005
Springer
Any computational approach to design, including the use of evolutionary algorithms, requires the transformation of the domain-specific knowledge into a formal design representatio...
DAGSTUHL
2006
13 years 12 months ago
2006
This paper presents a method of constructing pre-routed FPGA cores which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing sy...
DAC
1998
ACM
14 years 11 months ago
1998
ACM
The logic blocks CLBs of a lookup table LUT based FPGA consist of one or more LUTs, possibly of di erent sizes. In this paper, we focus on technology mapping for CLBs with several...
DATE
2000
IEEE
14 years 3 months ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
ICCAD
2005
IEEE
14 years 7 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...