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EUROPAR
2008
Springer
13 years 9 months ago
Optimized Pipelined Parallel Merge Sort on the Cell BE
Chip multiprocessors designed for streaming applications such as Cell BE offer impressive peak performance but suffer from limited bandwidth to offchip main memory. As the number o...
Jörg Keller, Christoph W. Kessler
CODES
2005
IEEE
14 years 1 months ago
Satisfying real-time constraints with custom instructions
Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application...
Pan Yu, Tulika Mitra
DAC
2006
ACM
14 years 8 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
INFOCOM
2007
IEEE
14 years 1 months ago
Two-Tier Load Balancing in OSPF Wireless Back-Hauls
Abstract— High-speed wireless communication technology (e.g. WiMAX) makes it feasible and cost-effective to build wireless back-hauls for Internet access. Compared to wired count...
Xiaowen Zhang, Hao Zhu
ICCAD
2003
IEEE
129views Hardware» more  ICCAD 2003»
14 years 22 days ago
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
Ruibing Lu, Cheng-Kok Koh