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» An architectural exploration of via patterned gate arrays
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DAC
2004
ACM
14 years 27 days ago
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
FPGA
2005
ACM
156views FPGA» more  FPGA 2005»
14 years 1 months ago
Design of programmable interconnect for sublithographic programmable logic arrays
Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional...
André DeHon
DATE
2005
IEEE
168views Hardware» more  DATE 2005»
14 years 1 months ago
Hardware Acceleration of Hidden Markov Model Decoding for Person Detection
This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent st...
Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 1 months ago
Assessing carbon nanotube bundle interconnect for future FPGA architectures
Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process techno...
Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen,...
DAC
2003
ACM
14 years 8 months ago
Using estimates from behavioral synthesis tools in compiler-directed design space exploration
This paper considers the role of performance and area estimates from behavioral synthesis in design space exploration. We have developed a compilation system that automatically ma...
Byoungro So, Pedro C. Diniz, Mary W. Hall