302 search results - page 4 / 61 » Automatic Verification of Timed Circuits |
ICCAD
1999
IEEE
14 years 2 months ago
1999
IEEE
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...
DAC
2002
ACM
14 years 10 months ago
2002
ACM
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
FORMATS
2006
Springer
14 years 1 months ago
2006
Springer
Using a variant of Clariso-Cortadella's parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of so...
ASPDAC
2010
ACM
13 years 7 months ago
2010
ACM
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
ATVA
2004
Springer
14 years 3 months ago
2004
Springer
