233 search results - page 8 / 47 » Balance Testing of Logic Circuits |
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
CHES
2003
Springer
14 years 21 days ago
2003
Springer
Abstract. Balanced asynchronous circuits have been touted as a superior replacement for conventional synchronous circuits. To assess these claims, we have designed, manufactured an...
FPGA
1997
ACM
13 years 11 months ago
1997
ACM
Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the ...
ITC
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...