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ETS
2006
IEEE
119views Hardware» more  ETS 2006»
14 years 3 months ago
On-Chip Test Generation Using Linear Subspaces
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses l...
Ramashis Das, Igor L. Markov, John P. Hayes
ICCAD
2006
IEEE
132views Hardware» more  ICCAD 2006»
14 years 3 months ago
Clock buffer polarity assignment for power noise reduction
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
Rupak Samanta, Ganesh Venkataraman, Jiang Hu
VTS
2005
IEEE
84views Hardware» more  VTS 2005»
14 years 2 months ago
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies
We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) a...
Ilia Polian, Sandip Kundu, Jean Marc Galliè...
ASPDAC
2004
ACM
97views Hardware» more  ASPDAC 2004»
14 years 2 months ago
Interconnect design methods for memory design
- This paper presents a solution to the problem of designing interconnects for memory devices. More precisely, it solves the automatic routing problem of memory peripheral circuits...
Chanseok Hwang, Massoud Pedram
DAC
2004
ACM
14 years 2 months ago
A new state assignment technique for testing and low power
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feed...
Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J....