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VLSID
2009
IEEE
223views VLSI» more  VLSID 2009»
14 years 8 months ago
Novel MOS Decoupling Capacitor Optimization Technique for Nanotechnologies
Designing MOS decoupling capacitors (DECAPs) in nanotechnologies provides many challenges due to the existing trade-offs among transient time response behavior, area, and gate lea...
Bardia Bozorgzadeh, Ali Afzali-Kusha
ISLPED
2007
ACM
117views Hardware» more  ISLPED 2007»
13 years 9 months ago
Power signal processing: a new perspective for power analysis and optimization
To address the productivity bottlenecks in power analysis and optimization of modern systems, we propose to treat power as a signal and leverage the rich set of signal processing ...
Quming Zhou, Lin Zhong, Kartik Mohanram
ISPD
2010
ACM
249views Hardware» more  ISPD 2010»
14 years 2 months ago
A matching based decomposer for double patterning lithography
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...
Yue Xu, Chris Chu
TVLSI
2010
13 years 2 months ago
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
Rupak Samanta, Jiang Hu, Peng Li
DAC
2004
ACM
14 years 8 months ago
Circuit-aware architectural simulation
Architectural simulation has achieved a prominent role in the system design cycle by providing designers the ability to quickly examine a wide variety of design choices. However, ...
Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Tod...