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DAC
2004
ACM
14 years 8 months ago
Post-layout logic optimization of domino circuits
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
Aiqun Cao, Cheng-Kok Koh
DAC
2006
ACM
14 years 8 months ago
Criticality computation in parameterized statistical timing
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswa...
DATE
2006
IEEE
116views Hardware» more  DATE 2006»
14 years 1 months ago
Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation
This paper presents a systematic and optimal design of hybrid cascode compensation method which is used in fully differential two-stage CMOS operational transconductance amplifier...
Mohammad Yavari, Omid Shoaei, Ángel Rodr&ia...
VISUALIZATION
2000
IEEE
14 years 16 hour ago
Navigating high-dimensional spaces to support design steering
Throughout the design cycle, visualization, whether a sketch scribbled on the back of a spare piece of paper or a fully detailed drawing, has been the mainstay of design: we need ...
Helen Wright, Ken Brodlie, Tim David
DAC
2006
ACM
14 years 8 months ago
Design space exploration using time and resource duality with the ant colony optimization
Design space exploration during high level synthesis is often conducted through ad-hoc probing of the solution space using some scheduling algorithm. This is not only time consumi...
Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastne...