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» Customized on-chip memories for embedded chip multiprocessor...
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CODES
2006
IEEE
14 years 2 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 1 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
HPCA
2009
IEEE
14 years 9 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
LPNMR
2009
Springer
14 years 3 months ago
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
Harold Ishebabi, Philipp Mahr, Christophe Bobda, M...
CODES
2007
IEEE
14 years 3 months ago
A data protection unit for NoC-based architectures
Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related...
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic...