103 search results - page 12 / 21 » DPA Leakage Models for CMOS Logic Circuits |
ISCAS
2003
IEEE
14 years 25 days ago
2003
IEEE
Abstract - A comprehensive study of ultra high-speed currentmode logic (CML) buffers and regenerative CML latches will be illustrated. A new design procedure to systematically desi...
PATMOS
2005
Springer
14 years 1 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
CHES
2006
Springer
13 years 11 months ago
2006
Springer
Recent research has shown that cryptographers with glitches are vulnerable in front of Side Channel Attacks (SCA). Since then, several methods, such as Wave Dynamic Differential Lo...
ISLPED
1996
ACM
13 years 11 months ago
1996
ACM
We present a new gate-level approach to current simulation. We use a symbolic model of current pulses that takes accurately into account the dependence on the switching conditions...
PATMOS
2004
Springer
14 years 27 days ago
2004
Springer
The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold l...