103 search results - page 7 / 21 » DPA Leakage Models for CMOS Logic Circuits |
ARVLSI
2001
IEEE
13 years 11 months ago
2001
IEEE
As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltag...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. This trend leads to potential vulnerabilities from untrusted circui...
ISQED
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimiza...
DAC
1999
ACM
13 years 12 months ago
1999
ACM
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...