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» Data partitioning on chip multiprocessors
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ASPDAC
2007
ACM
101views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
Abstract--An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed method...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
DAC
2008
ACM
13 years 11 months ago
Application mapping for chip multiprocessors
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...
Guangyu Chen, Feihui Li, Seung Woo Son, Mahmut T. ...
DATE
2009
IEEE
137views Hardware» more  DATE 2009»
14 years 4 months ago
Adaptive prefetching for shared cache based chip multiprocessors
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...
Mahmut T. Kandemir, Yuanrui Zhang, Ozcan Ozturk
ISCA
2006
IEEE
182views Hardware» more  ISCA 2006»
14 years 3 months ago
Cooperative Caching for Chip Multiprocessors
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...
Jichuan Chang, Gurindar S. Sohi
VLSID
2008
IEEE
151views VLSI» more  VLSID 2008»
14 years 10 months ago
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
Worst-case execution time (WCET) analysis and, in general, the predictability of real-time applications implemented on multiprocessor systems has been addressed only in very restri...
Alexandru Andrei, Petru Eles, Zebo Peng, Jakob Ros...