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122
Voted
DATE
1997
IEEE
15 years 7 months ago
1997
IEEE
A structural, fault-model based methodology for the generation of compact high-quality test sets for analog macros is presented. Results are shown for an IVconverter macro design....
145
Voted
DATE
2009
IEEE
15 years 7 months ago
2009
IEEE
Side channel attacks are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of triple rail logic agains...
105
Voted
DATE
2004
IEEE
15 years 7 months ago
2004
IEEE
Abstract-- Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing ca...
140
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DATE
2004
IEEE
15 years 7 months ago
2004
IEEE
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current funct...
115
Voted
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper proposes a novel architecture synthesis algorithm for single-loop single-bit ∆Σ modulators. We defined a generic modulator architecture and derived its noise and si...