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DATE
2007
IEEE
106views Hardware» more  DATE 2007»
14 years 3 months ago
Design closure driven delay relaxation based on convex cost network flow
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
Chuan Lin, Aiguo Xie, Hai Zhou
DATE
2006
IEEE
71views Hardware» more  DATE 2006»
14 years 2 months ago
Exploring "temperature-aware" design in low-power MPSoCs
The power density inside high performance systems continues to rise with every process technology generation, thereby increasing the operating temperature and creating “hot spot...
Giacomo Paci, Paul Marchal, Francesco Poletti, Luc...
DATE
2005
IEEE
169views Hardware» more  DATE 2005»
14 years 2 months ago
Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems
In this paper we present an approach to the design optimization of faulttolerant embedded systems for safety-critical applications. Processes are statically scheduled and communic...
Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Pe...
DATE
2003
IEEE
86views Hardware» more  DATE 2003»
14 years 2 months ago
A Top-Down Microsystems Design Methodology and Associated Challenges
An overview of microsystems technology is presented along with a discussion of the recent trends and challenges associated with its development. A typical bottom-up design methodo...
Michael S. McCorquodale, Fadi H. Gebara, Keith L. ...
DATE
2010
IEEE
124views Hardware» more  DATE 2010»
14 years 1 months ago
Control network generator for latency insensitive designs
—Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations h...
Eliyah Kilada, Kenneth S. Stevens