138 search results - page 5 / 28 » Delay modeling and static timing analysis for MTCMOS circuit... |
ISPD
2000
ACM
14 years 3 months ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
ISCAS
2005
IEEE
14 years 4 months ago
2005
IEEE
—As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for hig...
ITC
2003
IEEE
14 years 4 months ago
2003
IEEE
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
VLSID
2004
IEEE
14 years 11 months ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
ICCAD
2006
IEEE
14 years 7 months ago
2006
IEEE
Abstract—Manufacturing process variations lead to circuit timing variability and a corresponding timing yield loss. Traditional corner analysis consists of checking all process c...