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» Design and evaluation of an auto-memoization processor
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MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 1 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
EURODAC
1994
IEEE
116views VHDL» more  EURODAC 1994»
13 years 12 months ago
A performance evaluator for parameterized ASIC architectures
System-levelpartitioning assigns functionalobjects such as tasks or code segments to system-level components such as o-the-shelf processors or application-speci c architectures in...
Jie Gong, Daniel D. Gajski, Alex Nicolau
HPCA
2002
IEEE
14 years 8 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....
ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
14 years 4 months ago
Exploring the interplay of yield, area, and performance in processor caches
The deployment of future deep submicron technology calls for a careful review of existing cache organizations and design practices in terms of yield and performance. This paper pr...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 5 months ago
AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors
Soft error reliability is increasingly becoming a first-order design concern for microprocessors, as a result of higher transistor counts, shrinking device geometries and lowering ...
Arun A. Nair, Lizy Kurian John, Lieven Eeckhout