195 search results - page 14 / 39 » Design of clocked circuits using UML |
ISCA
2000
IEEE
14 years 6 days ago
2000
IEEE
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor ...
MICRO
2003
IEEE
14 years 1 months ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
GLVLSI
2010
IEEE
14 years 28 days ago
2010
IEEE
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
This paper discusses the use of networks-on-chip (NoCs) consisting of multiple voltage-frequency islands to cope with power consumption, clock distribution and parameter variation...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
—As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for hig...