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VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
14 years 7 months ago
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
Shabbir H. Batterywala, Narendra V. Shenoy
FPGA
2005
ACM
95views FPGA» more  FPGA 2005»
14 years 1 months ago
The Stratix II logic and routing architecture
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be p...
David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaugh...
DAC
2008
ACM
13 years 9 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik
TVLSI
2010
13 years 2 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
ICCAD
2001
IEEE
100views Hardware» more  ICCAD 2001»
14 years 4 months ago
Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. T...
Kaustav Banerjee, Amit Mehrotra