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ICES
2003
Springer
86views Hardware» more  ICES 2003»
14 years 2 months ago
A Note on Designing Logical Circuits Using SAT
Abstract. We present a systematic procedure for the synthesis and minimisation of digital circuits using propositional satisfiability. We encode the truth table into a canonical s...
Giovani Gomez Estrada
DSD
2002
IEEE
86views Hardware» more  DSD 2002»
14 years 2 months ago
Using Formal Tools to Study Complex Circuits Behaviour
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. The...
Paul Amblard, Fabienne Lagnier, Michel Lévy
ICES
2000
Springer
91views Hardware» more  ICES 2000»
14 years 19 days ago
Dynamic Optimisation of Non-linear Feed Forward Circuits
Abstract. An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16-bit address space into an 8-bit one. The target technolog...
Ernesto Damiani, Valentino Liberali, Andrea Tettam...
IOLTS
2006
IEEE
84views Hardware» more  IOLTS 2006»
14 years 3 months ago
Fault Tolerant System Design Method Based on Self-Checking Circuits
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity p...
Pavel Kubalík, Petr Fiser, Hana Kubatova
ISMVL
1999
IEEE
133views Hardware» more  ISMVL 1999»
14 years 1 months ago
Ternary Multiplication Circuits Using 4-Input Adder Cells and Carry Look-Ahead
We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary m...
Andreas Herrfeld, Siegbert Hentschke