Abstract. We present a systematic procedure for the synthesis and minimisation of digital circuits using propositional satisfiability. We encode the truth table into a canonical s...
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. The...
Abstract. An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16-bit address space into an 8-bit one. The target technolog...
Ernesto Damiani, Valentino Liberali, Andrea Tettam...
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity p...
We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary m...