122 search results - page 18 / 25 » Energy reduction in multiprocessor systems using transaction... |
ISCA
2010
IEEE
13 years 9 months ago
2010
IEEE
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
FPL
2004
Springer
13 years 11 months ago
2004
Springer
A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementin...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract-- Many of us in the field of ultra-low-Vdd processors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper i...
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
3DIC
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...