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ASPDAC
2009
ACM
133views Hardware» more  ASPDAC 2009»
13 years 11 months ago
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor
Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations a...
Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiro...
DAC
2003
ACM
14 years 10 months ago
Instruction encoding synthesis for architecture exploration using hierarchical processor models
This paper presents a novel instruction encoding generation technique for use in architecture exploration for application specific processors. The underlying exploration methodolo...
Achim Nohl, Volker Greive, Gunnar Braun, Andreas H...
PATMOS
2004
Springer
14 years 3 months ago
Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors
Abstract. An extensible and configurable processor is a programmable platform offering the possibility to customize the instruction set and/or underlying microarchitecture. Efficie...
Nikolaos Kavvadias, Spiridon Nikolaidis
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
14 years 3 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
DAC
1992
ACM
14 years 1 months ago
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
Ing-Jer Huang, Alvin M. Despain