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ICCAD
1996
IEEE
94views Hardware» more  ICCAD 1996»
14 years 2 months ago
Metrology for analog module testing using analog testability bus
In this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic eects in an analog testability bus test environment. For the test response...
Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tz...
ASPDAC
2007
ACM
107views Hardware» more  ASPDAC 2007»
14 years 2 months ago
Advanced tools for simulation and design of oscillators/PLLs
We present a robust, automated oscillator macromodeling technique for extracting comprehensive phase and amplitude macromodels from oscillators' SPICE circuit descriptions. Th...
Xiaolue Lai, Jaijeet S. Roychowdhury
AUSAI
2007
Springer
14 years 2 months ago
Weight Redistribution for Unweighted MAX-SAT
Many real-world problems are over-constrained and require search techniques adapted to optimising cost functions rather than searching for consistency. This makes the MAX-SAT probl...
Abdelraouf Ishtaiwi, John Thornton, Abdul Sattar
VLSID
2010
IEEE
211views VLSI» more  VLSID 2010»
14 years 2 months ago
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM
A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nanoCMOS static random access memory (SRAM) is presented. A 45nm single-end...
Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dh...
APCCAS
2006
IEEE
373views Hardware» more  APCCAS 2006»
14 years 1 months ago
A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs
A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair compa...
Vipul Katyal, Randall L. Geiger, Degang Chen