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VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 7 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
ICCD
2007
IEEE
121views Hardware» more  ICCD 2007»
14 years 4 months ago
Fast power network analysis with multiple clock domains
This paper proposes an efficient analysis flow and an algorithm to identify the worst case noise for power networks with multiple clock domains. First, we apply the Laplace transf...
Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Z...
ICCAD
2004
IEEE
128views Hardware» more  ICCAD 2004»
14 years 4 months ago
Power estimation for cycle-accurate functional descriptions of hardware
— Cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent in...
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj...
DATE
2009
IEEE
168views Hardware» more  DATE 2009»
14 years 2 months ago
Selective state retention design using symbolic simulation
Abstract—Addressing both standby and active power is a major challenge in developing System-on-Chip designs for batterypowered products. Powering off sections of logic or memorie...
Ashish Darbari, Bashir M. Al-Hashimi, David Flynn,...
ISCAS
2006
IEEE
133views Hardware» more  ISCAS 2006»
14 years 1 months ago
A psychiatric patients tracking system
This paper presents an RFID based psychiatric critical to psychiatric patient treatment. The work oftracking patient tracking system in a psychiatric patient care center. In psychi...
Ming-Hua Tsai, Chieh-Ling Huang, Pau-Choo Chung, Y...