27 search results - page 3 / 6 » Guiding Circuit Level Fault-Tolerance Design with Statistica... |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
— Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the cor...
DATE
1999
IEEE
14 years 7 days ago
1999
IEEE
If real number calculations are implemented as circuits, only a limited preciseness can be obtained. Hence, formal verification can not be used to prove the equivalence between th...
DAC
1998
ACM
14 years 9 months ago
1998
ACM
In this paper we present a statistical method for estimating the maximum power consumption in VLSI circuits. The method is based on the theory of extreme order statistics applied ...
DAC
2004
ACM
14 years 9 months ago
2004
ACM
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
DAC
2007
ACM
13 years 12 months ago
2007
ACM
This paper presents a statistical framework to cooperatively design and develop technology, product circuit, benchmarking and model early in the development stage. The statistical...