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ASAP
2000
IEEE
90views Hardware» more  ASAP 2000»
14 years 1 months ago
Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures
MicroSIMD architectures incorporating subword parallelism are very efficient for application-specific media processors as well as for fast multimedia information processing in gen...
Ruby B. Lee
ICCD
2006
IEEE
104views Hardware» more  ICCD 2006»
14 years 5 months ago
Guiding Architectural SRAM Models
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
Banit Agrawal, Timothy Sherwood
DATE
2005
IEEE
116views Hardware» more  DATE 2005»
14 years 2 months ago
A Complete Network-On-Chip Emulation Framework
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-OnChip (NoC) provide a structured way of realizing interconnections on silic...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
VTS
2005
IEEE
151views Hardware» more  VTS 2005»
14 years 2 months ago
A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers
: This project involves the design of a CMOS RF RMS Detector that converts the RMS voltage amplitude of an RF signal to a DC voltage. Its high input impedance and small area make i...
Alberto Valdes-Garcia, Radhika Venkatasubramanian,...
HPCA
2006
IEEE
14 years 9 months ago
Probabilistic counter updates for predictor hysteresis and stratification
Hardware counters are a fundamental building block of modern high-performance processors. This paper explores two applications of probabilistic counter updates, in which the outpu...
Nicholas Riley, Craig B. Zilles