238 search results - page 2 / 48 » Hierarchical Interconnect Circuit Models |
DAC
2002
ACM
14 years 8 months ago
2002
ACM
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
ISQED
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents a novel compact passive modeling technique for high-performance RF passives and interconnects modeled as high-order RLCM circuits. The new method is based on a...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper, we propose an efficient model order reduction (MOR) algorithm, called MTermMOR, for modeling interconnect circuits with large number of external ports. The prop...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—This paper presents an accurate interconnect thermal model for analyzing the temperature distribution of an on-chip interconnect wire. The model addresses the ambient te...