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ISSS
2002
IEEE
176views Hardware» more  ISSS 2002»
14 years 18 days ago
Controller Estimation for FPGA Target Architectures during High-Level Synthesis
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
FPL
2000
Springer
116views Hardware» more  FPL 2000»
13 years 11 months ago
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs
Abstract. Field-programmable gate arrays (FPGAs) have become increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercia...
Rolf Enzler, Tobias Jeger, Didier Cottet, Gerhard ...
DAC
1994
ACM
13 years 11 months ago
Memory Estimation for High Level Synthesis
Abstract -- This paper describes a new memory estimation technique for DSP applications written in an applicative language. Since no concept of storage is present in an applicative...
Ingrid Verbauwhede, Chris J. Scheers, Jan M. Rabae...
DATE
2002
IEEE
101views Hardware» more  DATE 2002»
14 years 20 days ago
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization
This paper presents a novel Energy-Aware Compilation (EAC) framework that can estimate and optimize energy consumption of a given code taking as input the architectural and techno...
Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vija...
GLVLSI
2000
IEEE
104views VLSI» more  GLVLSI 2000»
14 years 3 days ago
A new technique for estimating lower bounds on latency for high level synthesis
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
Helvio P. Peixoto, Margarida F. Jacome