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TVLSI
2010
13 years 3 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
DAC
2008
ACM
14 years 9 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...
VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
14 years 2 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran
FPL
2009
Springer
162views Hardware» more  FPL 2009»
14 years 2 days ago
Efficient particle-pair filtering for acceleration of molecular dynamics simulation
The acceleration of molecular dynamics (MD) simulations using high performance reconfigurable computing (HPRC) has been much studied. Given the intense competition from multicore...
Matt Chiu, Martin C. Herbordt
ICCS
2009
Springer
14 years 3 months ago
GPU Accelerated RNA Folding Algorithm
Many bioinformatics studies require the analysis of RNA or DNA structures. More specifically, extensive work is done to elaborate efficient algorithms able to predict the 2-D fold...
Guillaume Rizk, Dominique Lavenier