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ICCAD
2007
IEEE
91views Hardware» more  ICCAD 2007»
14 years 4 months ago
Variation-aware task allocation and scheduling for MPSoC
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. As a result, a paradigm shift from determ...
Feng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia W...
DAC
2001
ACM
14 years 8 months ago
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
Jason Cong, Michail Romesis
VLSID
2003
IEEE
167views VLSI» more  VLSID 2003»
14 years 8 months ago
Timing Minimization by Statistical Timing hMetis-based Partitioning
In this paper we present statistical timing driven hMetisbased partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing cri...
Cristinel Ababei, Kia Bazargan
ICCAD
2005
IEEE
97views Hardware» more  ICCAD 2005»
14 years 4 months ago
DiCER: distributed and cost-effective redundancy for variation tolerance
— Increasingly prominent variational effects impose imminent threat to the progress of VLSI technology. This work explores redundancy, which is a well-known fault tolerance techn...
Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, ...
ISVLSI
2008
IEEE
142views VLSI» more  ISVLSI 2008»
14 years 2 months ago
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing
In nanometer regime, the effects of process variations are dominating circuit performance, power and reliability of circuits. Hence, it is important to properly manage variation e...
Venkataraman Mahalingam, Nagarajan Ranganathan