154 search results - page 20 / 31 » Interconnect Optimization Strategies for High-Performance VL... |
DAC
2007
ACM
14 years 11 months ago
2007
ACM
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
ISCAS
1999
IEEE
14 years 2 months ago
1999
IEEE
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
FCCM
2009
IEEE
14 years 2 months ago
2009
IEEE
FPGA has long been considered an attractive platform for high performance implementations of string matching. However, as the size of pattern dictionaries continues to grow, such ...
DAC
1996
ACM
14 years 2 months ago
1996
ACM
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
VLSID
2006
IEEE
14 years 10 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...