731 search results - page 19 / 147 » Interconnect modeling for improved system-level design optim... |
ICPP
2000
IEEE
13 years 12 months ago
2000
IEEE
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We de ne a class of optimization problems as CH-posynomial programs and reveal a genera...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...
DATE
2003
IEEE
14 years 25 days ago
2003
IEEE
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
MICRO
2002
IEEE
14 years 14 days ago
2002
IEEE
With the prevalence of server blades and systems-ona-chip (SoCs), interconnection networks are becoming an important part of the microprocessor landscape. However, there is limite...