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    » Interconnecting Computers: Architecture, Technology, and Eco...
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    EDCC
    2008
    Springer
    123views Applied Computing» more  EDCC 2008»
    A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR
    13 years 10 months ago
    A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR
    Download  www.vmars.tuwien.ac.at
    The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...
    Roman Obermaisser, Hubert Kraut, Christian El Sall...
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    JUCS
    2006
    112views more  JUCS 2006»
    A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
    13 years 8 months ago
    A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
    Download  www.jucs.org
    Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
    Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
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    DAC
    2005
    ACM
    109views Computer Architecture» more  DAC 2005»
    Device and architecture co-optimization for FPGA power reduction
    14 years 9 months ago
    Device and architecture co-optimization for FPGA power reduction
    Download  www.ee.ucla.edu
    Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
    Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
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    DATE
    2006
    IEEE
    123views Hardware» more  DATE 2006»
    Networks on chips for high-end consumer-electronics TV system architectures
    14 years 2 months ago
    Networks on chips for high-end consumer-electronics TV system architectures
    Download  homepages.inf.ed.ac.uk
    Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SO...
    Frits Steenhof, Harry Duque, Björn Nilsson, K...
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    SC
    2009
    ACM
    226views Applied Computing» more  SC 2009»
    Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications
    14 years 3 months ago
    Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications
    Download  www.nas.nasa.gov
    In this paper, we present an early performance evaluation of a 624-core cluster based on the Intel® Xeon® Processor 5560 (code named “Nehalem-EP”, and referred to as Xeon 55...
    Subhash Saini, Andrey Naraikin, Rupak Biswas, Davi...
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