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ISCAS
2007
IEEE
167views Hardware» more  ISCAS 2007»
14 years 2 months ago
An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM
— Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells in standby mode reduces the leakage curren...
Afshin Nourivand, Chunyan Wang, M. Omair Ahmad
CODES
2007
IEEE
14 years 2 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
14 years 1 months ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
DSD
2010
IEEE
161views Hardware» more  DSD 2010»
13 years 8 months ago
Design of Trace-Based Split Array Caches for Embedded Applications
—Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to o...
Alice M. Tokarnia, Marina Tachibana
DATE
2006
IEEE
93views Hardware» more  DATE 2006»
14 years 2 months ago
Restructuring field layouts for embedded memory systems
In many computer systems with large data computations, the delay of memory access is one of the major performance bottlenecks. In this paper, we propose an enhanced field remappi...
Keoncheol Shin, Jungeun Kim, Seonggun Kim, Hwansoo...