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» Linking codesign and reuse in embedded systems design
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CODES
2004
IEEE
13 years 11 months ago
Power-aware communication optimization for networks-on-chips with voltage scalable links
Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energyefficient static algorithm which optimizes the ener...
Dongkun Shin, Jihong Kim
CODES
2005
IEEE
14 years 1 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
CODES
2006
IEEE
13 years 11 months ago
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel suppo...
Hayden Kwok-Hay So, Artem Tkachenko, Robert W. Bro...
CODES
2003
IEEE
14 years 1 months ago
Deriving process networks from weakly dynamic applications in system-level design
We present an approach to the automatic derivation of executable Process Network specifications from Weakly Dynamic Applications. We introduce the notions of Dynamic Single Assig...
Todor Stefanov, Ed F. Deprettere
CODES
2007
IEEE
14 years 2 months ago
Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions
High-end biomedical applications are a good target for specificpurpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring and analysis ...
Iyad Al Khatib, Davide Bertozzi, Axel Jantsch, Luc...