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CODES
2005
IEEE
14 years 2 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ICALT
2005
IEEE
14 years 2 months ago
ActiveTutor
In this paper we present an architecture dedicated to an intelligently assisted educational tool which integrates within a unified framework software rational agents both at the m...
Jean Pierre Fournier
IEEEPACT
2005
IEEE
14 years 2 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
VISUALIZATION
2005
IEEE
14 years 2 months ago
Query-Driven Visualization of Large Data Sets
We present a practical and general-purpose approach to large and complex visual data analysis where visualization processing, rendering and subsequent human interpretation is cons...
Kurt Stockinger, John Shalf, Kesheng Wu, E. Wes Be...
WACV
2005
IEEE
14 years 2 months ago
Integrating Range and Texture Information for 3D Face Recognition
The performance of face recognition systems that use two-dimensional images depends on consistent conditions w.r.t. lighting, pose, and facial appearance. We are developing a face...
Xiaoguang Lu, Anil K. Jain
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