3799 search results - page 25 / 760 » Low Power or High Performance |
105
Voted
ICCD
2006
IEEE
16 years 16 days ago
2006
IEEE
—X-filling is preferred for low-capture-power scan test generation, since it reduces IR-drop-induced yield loss without the need of any circuit modification. However, the effecti...
117
Voted
ICCD
2006
IEEE
16 years 16 days ago
2006
IEEE
— In this paper, we present two designs for CMOS comparators: one which is targeted for high-speed applications and another for low-power applications. Additionally, we present h...
110
click to vote
ICCD
2008
IEEE
15 years 10 months ago
2008
IEEE
— SRAMs typically represent half of the area and more than half of the transistors on a chip today. Variability increases as feature size decreases, and the impact of variability...
86
Voted
ASPDAC
2007
ACM
15 years 7 months ago
2007
ACM
- The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...
160
Voted
ISVLSI
2002
IEEE
15 years 8 months ago
2002
IEEE
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...