1004 search results - page 31 / 201 » Low power methodology and design techniques for processor de... |
DAC
2002
ACM
14 years 9 months ago
2002
ACM
This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput ...
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing a new processor architecture, as well as when evaluating the ...
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
ISLPED
2007
ACM
13 years 10 months ago
2007
ACM
Dynamic voltage scaling (DVS) is known to be one of the most efficient techniques for power reduction of integrated circuits. Efficient low voltage DC-DC conversion is a key enabl...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Technological advances enable modern processors to utilize increasingly larger DRAMs with rising access frequencies. This is leading to high power consumption and operating temper...