1004 search results - page 6 / 201 » Low power methodology and design techniques for processor de... |
DAC
2010
ACM
14 years 10 days ago
2010
ACM
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
— Design and analysis guidelines for resonant interconnect networks are presented in this paper. The methodology focuses on developing an accurate analytic distributed model of t...
ASPDAC
2008
ACM
13 years 10 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
GLVLSI
2006
IEEE
14 years 2 months ago
2006
IEEE
Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology base...
ITC
2000
IEEE
14 years 24 days ago
2000
IEEE
