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» Modeling Cache Sharing on Chip Multiprocessor Architectures
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GLVLSI
2007
IEEE
154views VLSI» more  GLVLSI 2007»
14 years 3 months ago
A design kit for a fully working shared memory multiprocessor on FPGA
This paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template ar...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...
HPCA
2005
IEEE
14 years 9 months ago
Improving Multiple-CMP Systems Using Token Coherence
Improvements in semiconductor technology now enable Chip Multiprocessors (CMPs). As many future computer systems will use one or more CMPs and support shared memory, such systems ...
Michael R. Marty, Jesse D. Bingham, Mark D. Hill, ...
HPCA
2006
IEEE
14 years 9 months ago
Exploiting parallelism and structure to accelerate the simulation of chip multi-processors
Simulation is an important means of evaluating new microarchitectures. Current trends toward chip multiprocessors (CMPs) try the ability of designers to develop efficient simulato...
David A. Penry, Daniel Fay, David Hodgdon, Ryan We...
MICRO
2008
IEEE
148views Hardware» more  MICRO 2008»
14 years 3 months ago
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach
—Efficient sharing of system resources is critical to obtaining high utilization and enforcing system-level performance objectives on chip multiprocessors (CMPs). Although sever...
Ramazan Bitirgen, Engin Ipek, José F. Mart&...
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 1 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita