78 search results - page 15 / 16 » Modeling QCA for area minimization in logic synthesis |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
ISLPED
2006
ACM
14 years 29 days ago
2006
ACM
This paper addresses the problem of low-power fanout optimization. We show that due to neglecting short-circuit current, previous analytical techniques proposed to optimize the ar...
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
ISQED
2005
IEEE
14 years 18 days ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...