1151 search results - page 35 / 231 » Modelling Digital Circuits Problems with Set Constraints |
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
ITC
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper demonstrates a system that performs multiobjective sizing across 100,000 analog circuit topologies simultaneously, with SPICE accuracy. It builds on a previous system, ...
CORR
2007
Springer
13 years 7 months ago
2007
Springer
— In order to optimize the costs and time of design of the new products while improving their quality, concurrent engineering is based on the digital model of these products, the...