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» Modelling Digital Circuits Problems with Set Constraints
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CAV
1990
Springer
114views Hardware» more  CAV 1990»
13 years 11 months ago
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
Ternary system modeling involves extending the traditional set of binary values
Randal E. Bryant, Carl-Johan H. Seger
VLSID
2003
IEEE
103views VLSI» more  VLSID 2003»
14 years 8 months ago
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
13 years 11 months ago
Optimization of critical paths in circuits with level-sensitive latches
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
Timothy M. Burks, Karem A. Sakallah
DATE
2003
IEEE
102views Hardware» more  DATE 2003»
14 years 28 days ago
Power Constrained High-Level Synthesis of Battery Powered Digital Systems
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
S. F. Nielsen, Jan Madsen
CG
2008
Springer
13 years 7 months ago
Masked photo blending: Mapping dense photographic data set on high-resolution sampled 3D models
The technological advance of sensors is producing an exponential size growth of the data coming from 3D scanning and digital photography. The production of digital 3D models consi...
Marco Callieri, Paolo Cignoni, Massimiliano Corsin...