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VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 10 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
14 years 10 months ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
14 years 10 months ago
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
Shabbir H. Batterywala, Narendra V. Shenoy
VLSID
2002
IEEE
151views VLSI» more  VLSID 2002»
14 years 10 months ago
Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems
Among the many techniques for system-level power management, it is not currently possible to guarantee timing constraints and have a comprehensive system model at the same time. S...
Dexin Li, Pai H. Chou, Nader Bagherzadeh
VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
14 years 10 months ago
Address Code and Arithmetic Optimizations for Embedded Systems
An important class of problems used widely in both the embedded systems and scientific domains perform memory intensive computations on large data sets. These data sets get to be ...
J. Ramanujam, Satish Krishnamurthy, Jinpyo Hong, M...
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