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» Noise-tolerant dynamic circuit design
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ICCD
2000
IEEE
88views Hardware» more  ICCD 2000»
14 years 5 months ago
Dynamic Flip-Flop with Improved Power
An improved design of a dynamic Flip-Flop is presented. Proposed design overcomes the problem of the glitch at the output and improves Power-Delay Product for about 10%, while pre...
Nikola Nedovic, Vojin G. Oklobdzija
ISLPED
2003
ACM
71views Hardware» more  ISLPED 2003»
14 years 1 months ago
Strained-si devices and circuits for low-power applications
Static and dynamic power for strained-Si device is analyzed and compared with conventional bulk-Si technology. Optimum device design points are suggested with controlling physical...
Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang
DAC
2006
ACM
14 years 9 months ago
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper t...
Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
ICCAD
2002
IEEE
124views Hardware» more  ICCAD 2002»
14 years 5 months ago
Interface specification for reconfigurable components
This paper presents a way of encoding some kinds of dynamic reconfiguration behaviour in the interface portion of circuit descriptions. This has many advantages. The user of a rec...
Satnam Singh
ASPDAC
2004
ACM
141views Hardware» more  ASPDAC 2004»
14 years 1 months ago
An approach for reducing dynamic power consumption in synchronous sequential digital designs
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
Noureddine Chabini, Wayne Wolf