339 search results - page 3 / 68 » Noise-tolerant dynamic circuit design |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
— This paper introduces a graph grammar based approach to automated topology synthesis of analog circuits. A grammar is developed to generate circuits through production rules, t...
ISCAS
1999
IEEE
13 years 11 months ago
1999
IEEE
-- Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energyefficiency o...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
: CMOS circuits have significant amounts of dynamic short-circuit (or through) current. This can be as large as 20% of the total in well-designed circuits, and up to 80% of the tot...
GECCO
2005
Springer
14 years 26 days ago
2005
Springer
This paper proposes and analyses the performance of a Genetic Algorithm (GA) using two new concepts, namely a static fitness function including a discontinuity measure and a fract...
VLSID
2004
IEEE
14 years 7 months ago
2004
IEEE
{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized b...